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COP/JTAG Port
Table 5-20. COP/JTAG Port Signals Description (continued)
Pin No.
9
Signal Name
TMS
Attribute
I
Description
Test Mode Select. This signal qualified with TCK in a same
manner as TDI, changes the state of the JTAG machine. This line
is pulled up internally by the PowerQUICC II.
10
11
N.C.
SRESET
-
I/O, O.D.
Not Connected.
Soft Reset (L). This is the PowerQUICC II’s soft reset which is in
fact a non-maskable interrupt, making the PowerPC take the
reset exception from the reset vector. This line may be driven by
the PowerQUICC II as well during soft-reset sequence, for 512
system clocks. This line is pulled up on the MPC8272ADS with a
1K ? resistor. When driven externally, it MUST be driven with an
Open Drain gate. Failure in doing so might result in
permanent damage to the PowerQUICC II and / or to board
logic.
12
13
GND
HRESET
O
I/O, O.D.
Digital GND. Main GND plane.
PowerQUICC II’s Hard Reset (L). When asserted by an external
H/W, generates Hard-Reset sequence for the PowerQUICC II.
During that sequence, asserted by the MPC for 512 system
clocks. Pulled Up on the MPC8272ADS using a 1K ? resistor.
When driven by an external tool, MUST be driven with an Open
Drain gate. Failure in doing so might result in permanent
damage to the PowerQUICC II and / or to board logic.
14
15
N.C.
XBR3
(CKSTOP_OUT)
-
I/O
Not Connected.
Normally configured as XBR3 which has no function with this
connector. May be configured as CKSTOP_OUT - Check Stop
Out (L). When asserted (Low) indicates that the PowerQUICC II
core has entered a Check-Stop state.
16
GND
O
Digital GND. Main GND plane.
Chapter 5. Module Design
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